Bibliometrics
Skip Table Of Content Section
SECTION: Special Section on Machine Learning for CAD/EDA
survey
A Comprehensive Survey on Electronic Design Automation and Graph Neural Networks: Theory and Applications
Article No.: 15, pp 1–27https://doi.org/10.1145/3543853

Driven by Moore’s law, the chip design complexity is steadily increasing. Electronic Design Automation (EDA) has been able to cope with the challenging very large-scale integration process, assuring scalability, reliability, and proper time-to-market. ...

research-article
A Survey and Perspective on Artificial Intelligence for Security-Aware Electronic Design Automation
Article No.: 16, pp 1–57https://doi.org/10.1145/3563391

Artificial intelligence (AI) and machine learning (ML) techniques have been increasingly used in several fields to improve performance and the level of automation. In recent years, this use has exponentially increased due to the advancement of high-...

research-article
Power Converter Circuit Design Automation Using Parallel Monte Carlo Tree Search
Article No.: 17, pp 1–33https://doi.org/10.1145/3549538

The tidal waves of modern electronic/electrical devices have led to increasing demands for ubiquitous application-specific power converters. A conventional manual design procedure of such power converters is computation- and labor-intensive, which ...

research-article
Machine Learning Assisted Circuit Sizing Approach for Low-Voltage Analog Circuits with Efficient Variation-Aware Optimization
Article No.: 18, pp 1–22https://doi.org/10.1145/3567422

Low-power analog design is a hot topic for various power efficient applications. Sizing low-power analog circuits is not easy because the increasing uncertainties from low-voltage techniques magnify process variation effects on the design yield. ...

research-article
Performance-driven Wire Sizing for Analog Integrated Circuits
Article No.: 19, pp 1–23https://doi.org/10.1145/3559542

Analog IC performance has a strong dependence on interconnect RC parasitics, which are significantly affected by wire sizes in recent technologies, where minimum-width wires have high resistance. However, performance-driven wire sizing for analog ICs has ...

research-article
Open Access
Machine-learning-driven Architectural Selection of Adders and Multipliers in Logic Synthesis
Article No.: 20, pp 1–16https://doi.org/10.1145/3560712

Designing high-performance adders and multiplier components for diverse specifications and constraints is of practical concern. However, selecting the best architecture for adder or multiplier, which largely affects the performance of synthesized circuits,...

research-article
GraphPlanner: Floorplanning with Graph Neural Network
Article No.: 21, pp 1–24https://doi.org/10.1145/3555804

Chip floorplanning has long been a critical task with high computation complexity in the physical implementation of VLSI chips. Its key objective is to determine the initial locations of large chip modules with minimized wirelength while adhering to the ...

research-article
Open Access
Efficient Test Chip Design via Smart Computation
Article No.: 22, pp 1–31https://doi.org/10.1145/3558393

Submitted to the Special Issue on Machine Learning for CAD (ML-CAD). Competitive strength in semiconductor field depends on yield. The challenges associated with designing and manufacturing of leading-edge integrated circuits (ICs) have increased that ...

research-article
Learning-based Phase-aware Multi-core CPU Workload Forecasting
Article No.: 23, pp 1–27https://doi.org/10.1145/3564929

Predicting workload behavior during workload execution is essential for dynamic resource optimization in multi-processor systems. Recent studies have proposed advanced machine learning techniques for dynamic workload prediction. Workload prediction can be ...

research-article
Machine Learning Based Framework for Fast Resource Estimation of RTL Designs Targeting FPGAs
Article No.: 24, pp 1–16https://doi.org/10.1145/3555047

Field-programmable gate arrays (FPGAs) have grown to be an important platform for integrated circuit design and hardware emulation. However, with the dramatic increase in design scale, it has become a key challenge to partition very large scale ...

research-article
Open Access
Graph Neural Networks for High-Level Synthesis Design Space Exploration
Article No.: 25, pp 1–20https://doi.org/10.1145/3570925

High-level Synthesis (HLS) Design-Space Exploration (DSE) aims at identifying Pareto-optimal synthesis configurations whose exhaustive search is unfeasible due to the design-space dimensionality and the prohibitive computational cost of the synthesis ...

research-article
Training PPA Models for Embedded Memories on a Low-data Diet
Article No.: 26, pp 1–24https://doi.org/10.1145/3556539

Supervised machine learning requires large amounts of labeled data for training. In power, performance, and area (PPA) estimation of embedded memories, every new memory compiler version is considered independently of previous compiler versions. Since the ...

research-article
BoA-PTA: A Bayesian Optimization Accelerated PTA Solver for SPICE Simulation
Article No.: 27, pp 1–26https://doi.org/10.1145/3555805

One of the greatest challenges in integrated circuit design is the repeated executions of computationally expensive SPICE simulations, particularly when highly complex chip testing/verification is involved. Recently, pseudo-transient analysis (PTA) has ...

SECTION: Regular Papers
research-article
Open Access
A Symbolic Approach to Detecting Hardware Trojans Triggered by Don’t Care Transitions
Article No.: 28, pp 1–31https://doi.org/10.1145/3558392

Due to the globalization of Integrated Circuit supply chain, hardware Trojans and the attacks that can trigger them have become an important security issue. One type of hardware Trojans leverages the “don’t care transitions” in Finite-state Machines (FSMs)...

research-article
Application Mapping and Control-system Design for Microfluidic Biochips with Distributed Channel Storage
Article No.: 29, pp 1–30https://doi.org/10.1145/3564288

Continuous-flow microfluidic biochips have emerged as a potential low-cost and fast-responsive lab-on-chip platform. They have attracted much attention due to their capability of performing various biochemical applications concurrently and automatically ...

Subjects

Comments

About Cookies On This Site

We use cookies to ensure that we give you the best experience on our website.

Learn more

Got it!