Volume 22, Issue 2March 2023Current Issue
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research-article
Application-centric Network Management - Addressing Safety and Real-time in V2X Applications
The current roadmaps and surveys for future wireless networking typically focus on communication and networking technologies and use representative applications to derive future network requirements. Such a benchmarking approach, however, does not cover ...
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Vector Extensions in COTS Processors to Increase Guaranteed Performance in Real-Time Systems
- Roger Pujol,
- Josep Jorba,
- Hamid Tabani,
- Leonidas Kosmidis,
- Enrico Mezzetti,
- Jaume Abella,
- Francisco Cazorla
The need for increased application performance in high-integrity systems such as those in avionics is on the rise as software continues to implement more complex functionalities. The prevalent computing solution for future high-integrity embedded products ...
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A Contrastive Plan Explanation Framework for Hybrid System Models
In artificial intelligence planning, having an explanation of a plan given by a planner is often desirable. The ability to explain various aspects of a synthesized plan to an end user not only brings in trust on the planner but also reveals insights of ...
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ETAP: Energy-aware Timing Analysis of Intermittent Programs
Energy harvesting battery-free embedded devices rely only on ambient energy harvesting that enables stand-alone and sustainable IoT applications. These devices execute programs when the harvested ambient energy in their energy reservoir is sufficient to ...
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Reconfigurable System-on-Chip Architectures for Robust Visual SLAM on Humanoid Robots
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High-Performance Implementation of the Identity-Based Signature Scheme in IEEE P1363 on GPU
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SAT-Reach: A Bounded Model Checker for Affine Hybrid Systems
Bounded model checking (BMC) is well-known to be undecidable even for simple hybrid systems. Existing work targeted for a wide class of non-linear hybrid systems reduces the BMC problem to the satisfiability problem of an satisfiability modulo theory ...
SECTION: Special Issue on Domain-Specific System-on-Chip Architectures and Run-Time Management Techniques
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Domain-Specific Architectures: Research Problems and Promising Approaches
Process technology-driven performance and energy efficiency improvements have slowed down as we approach physical design limits. General-purpose manycore architectures attempt to circumvent this challenge, but they have a significant performance and ...
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Experimental Demonstration of STT-MRAM-based Nonvolatile Instantly On/Off System for IoT Applications: Case Studies
Energy consumption has been a big challenge for electronic devices, particularly for battery-powered Internet of Things (IoT) equipment. To address such a challenge, on the one hand, low-power electronic design methodologies and novel power management ...
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SHARP: An Adaptable, Energy-Efficient Accelerator for Recurrent Neural Networks
The effectiveness of Recurrent Neural Networks (RNNs) for tasks such as Automatic Speech Recognition has fostered interest in RNN inference acceleration. Due to the recurrent nature and data dependencies of RNN computations, prior work has designed ...
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FARSI: An Early-stage Design Space Exploration Framework to Tame the Domain-specific System-on-chip Complexity
- Behzad Boroujerdian,
- Ying Jing,
- Devashree Tripathy,
- Amit Kumar,
- Lavanya Subramanian,
- Luke Yen,
- Vincent Lee,
- Vivek Venkatesan,
- Amit Jindal,
- Robert Shearer,
- Vijay Janapa Reddi
Domain-specific SoCs (DSSoCs) are an attractive solution for domains with extremely stringent power, performance, and area constraints. However, DSSoCs suffer from two fundamental complexities. On the one hand, their many specialized hardware blocks ...
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Early DSE and Automatic Generation of Coarse-grained Merged Accelerators
Post-Moore’s law area-constrained systems rely on accelerators to deliver performance enhancements. Coarse-grained accelerators can offer substantial domain acceleration, but manual, ad hoc identification of code to accelerate is prohibitively expensive. ...
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QUIDAM: A Framework for Quantization-aware DNN Accelerator and Model Co-Exploration
As the machine learning and systems communities strive to achieve higher energy efficiency through custom deep neural network (DNN) accelerators, varied precision or quantization levels, and model compression techniques, there is a need for design space ...
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HLS-based High-throughput and Work-efficient Synthesizable Graph Processing Template Pipeline
Hardware systems composed of diverse execution resources are being deployed to cope with the complexity and performance requirements of Artificial Intelligence (AI) and Machine Learning (ML) applications. With the emergence of new hardware platforms, ...
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AHA: An Agile Approach to the Design of Coarse-Grained Reconfigurable Accelerators and Compilers
- Kalhan Koul,
- Jackson Melchert,
- Kavya Sreedhar,
- Leonard Truong,
- Gedeon Nyengele,
- Keyi Zhang,
- Qiaoyi Liu,
- Jeff Setter,
- Po-Han Chen,
- Yuchen Mei,
- Maxwell Strange,
- Ross Daly,
- Caleb Donovick,
- Alex Carsello,
- Taeyoung Kong,
- Kathleen Feng,
- Dillon Huff,
- Ankita Nayak,
- Rajsekhar Setaluri,
- James Thomas,
- Nikhil Bhagdikar,
- David Durst,
- Zachary Myers,
- Nestan Tsiskaridze,
- Stephen Richardson,
- Rick Bahr,
- Kayvon Fatahalian,
- Pat Hanrahan,
- Clark Barrett,
- Mark Horowitz,
- Christopher Torng,
- Fredrik Kjolstad,
- Priyanka Raina
With the slowing of Moore’s law, computer architects have turned to domain-specific hardware specialization to continue improving the performance and efficiency of computing systems. However, specialization typically entails significant modifications to ...
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CEDR: A Compiler-integrated, Extensible DSSoC Runtime
In this work, we present a Compiler-integrated, Extensible Domain Specific System on Chip Runtime (CEDR) ecosystem to facilitate research toward addressing the challenges of architecture, system software, and application development with distinct plug-and-...
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AdaTest: Reinforcement Learning and Adaptive Sampling for On-chip Hardware Trojan Detection
This paper proposes AdaTest, a novel adaptive test pattern generation framework for efficient and reliable Hardware Trojan (HT) detection. HT is a backdoor attack that tampers with the design of victim integrated circuits (ICs). AdaTest improves the ...
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Virtualizing a Post-Moore’s Law Analog Mesh Processor: The Case of a Photonic PDE Accelerator
- Jeff Anderson,
- Engin Kayraklioglu,
- Hamid Reza Imani,
- Chen Shen,
- Mario Miscuglio,
- Volker J. Sorger,
- Tarek El-Ghazawi
Innovative processor architectures aim to play a critical role in future sustainment of performance improvements under severe limitations imposed by the end of Moore’s Law. The Reconfigurable Optical Computer (ROC) is one such innovative, Post-Moore’s Law ...
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A Predictable QoS-aware Memory Request Scheduler for Soft Real-time Systems
A memory controller manages the flow of data to and from attached memory devices. The order in which a set of contending memory requests from different tasks are serviced significantly influences the rate of progress and completion times of these tasks. ...