ABSTRACT
High-level hardware generators have significantly increased the productivity of design engineers. They use software engineering constructs to reduce the repetition required to express complex designs and enable more composability. However, these benefits are undermined by a lack of debugging infrastructure, requiring hardware designers to debug generated, usually incomprehensible, RTL code. This paper describes a framework that connects modern software source-level debugging frameworks to RTL created from hardware generators. Our working prototype offers an Integrated Development Environment (IDE) experience for generators such as RocketChip (Chisel), allowing designers to set breakpoints in complex source code, relate RTL simulation state back to source-level variables, and do forward and backward debugging, with almost no simulation overhead (less than 5%).
- Scott Beamer and David Donofrio. 2020. Efficiently exploiting low activity factors to accelerate RTL simulation. In DAC. ACM/IEEE, USA, 1--6.Google Scholar
- The DWARF committee. 2017. The DWARF Debugging Standard.Google Scholar
- Barry K Rosen, Mark N Wegman, and F Kenneth Zadeck. 1988. Global value numbers and redundant computations. In Proceedings of the 15th SIGPLAN-SIGACT symposium on Principles of programming languages. ACM, USA, 12--27.Google Scholar
Digital Library
- Synopsys. 2021. Verdi.Google Scholar
- S. Jiang el.al. 2018. Mamba: closing the performance gap in productive hardware development frameworks. In DAC. ACM/IEEE, USA, 1--6.Google Scholar
- A. Izraelevitz et al. 2017. Reusability is FIRRTL ground: Hardware construction languages, compiler frameworks, and transformations. In ICCAD. IEEE, USA, 209--216.Google Scholar
- David R Ditzel et al. 1980. Retrospective on high-level language computer architecture. In ISCA. ACM, USA, 97--104.Google Scholar
- J. Bachrach et al. 2012. Chisel: Constructing hardware in a Scala embedded language. In DAC. ACM/IEEE, USA, 1212--1221.Google Scholar
Digital Library
- Ofer Shacham et al. 2010. Rethinking digital design: Why design must change. IEEE micro 30, 6 (2010), 9--24.Google Scholar
- Young-Nam Yun et al. 2011. Beyond UVM for practical SoC verification. In International SoC Design Conference. IEEE, USA, 158--162.Google Scholar
- N. Calagar et.al. 2014. Source-level debugging for FPGA high-level synthesis. In FPL. IEEE, USA, 1--8.Google Scholar
- Leonard Truong and Pat Hanrahan. 2021. Magma circuits. https://github.com/phanrahan/magmaGoogle Scholar
Index Terms
Bringing source-level debugging frameworks to hardware generators
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