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Stanford University, Stanford, CA
,Stanford University, Stanford, CA
,Stanford University, Stanford, CA
,Stanford University, Stanford, CA
,Stanford University, Stanford, CA
,Stanford University, Stanford, CA
,Stanford University, Stanford, CA
,Stanford University, Stanford, CA
,Stanford University, Stanford, CA
,Stanford University, Stanford, CA
,Stanford University, Stanford, CA
To effectively minimize static power for a wide range of applications, power domains for coarse-grained reconfigurable array (CGRA) architectures need to be more fine-grained than those found in a typical application-specific integrated circuit. However, ...
Stanford University, USA
,Stanford University, USA
,Stanford University, USA
,Stanford University, USA
,Stanford University, USA
,Stanford University, USA
,Stanford University, USA
,Stanford University, USA
,Stanford University, USA
The architecture of a coarse-grained reconfigurable array (CGRA) processing element (PE) has a significant effect on the performance and energy-efficiency of an application running on the CGRA. This paper presents APEX, an automated approach for ...
Stanford University, USA
,Stanford University, USA
,Stanford University, USA
,Massachusetts Institute of Technology, USA
,Stanford University, USA
,Massachusetts Institute of Technology, USA / NVIDIA, USA
,Stanford University, USA
,Stanford University, USA
We propose the Sparse Abstract Machine (SAM), an abstract machine model for targeting sparse tensor algebra to reconfigurable and fixed-function spatial dataflow accelerators. SAM defines a streaming dataflow abstraction with sparse primitives that ...
Stanford University, Stanford, CA, USA
,Stanford University, Stanford, CA, USA
,Stanford University, Stanford, CA, USA
,Stanford University, Stanford, CA, USA
,Stanford University, Stanford, CA, USA
,Stanford University, Stanford, CA, USA
,Stanford University, Stanford, CA, USA
,Stanford University, Stanford, CA, USA
Image processing and machine learning applications benefit tremendously from hardware acceleration. Existing compilers target either FPGAs, which sacrifice power and performance for programmability, or ASICs, which become obsolete as applications change. ...
Stanford University, Stanford, California, USA
,Stanford University, Stanford, California, USA
,Stanford University, Stanford, California, USA
,Stanford University, Stanford, California, USA
,Stanford University, Stanford, California, USA
,Stanford University, Stanford, California, USA
,Stanford University, Stanford, California, USA
,Stanford University, Stanford, California, USA
,Stanford University, Stanford, California, USA
,Stanford University, Stanford, California, USA
,Stanford University, Stanford, California, USA
,Stanford University, Stanford, California, USA
,Stanford University, Stanford, California, USA
,Stanford University, Stanford, California, USA
,Stanford University, Stanford, California, USA
,Stanford University, Stanford, California, USA
,Stanford University, Stanford, California, USA
,Stanford University, Stanford, California, USA
,Stanford University, Stanford, California, USA
,Stanford University, Stanford, California, USA
,Stanford University, Stanford, California, USA
,Stanford University, Stanford, California, USA
,Stanford University, Stanford, California, USA
,Stanford University, Stanford, California, USA
,Stanford University, Stanford, California, USA
,Stanford University, Stanford, California, USA
,Stanford University, Stanford, California, USA
,Stanford University, Stanford, California, USA
,Stanford University, Stanford, California, USA
,Stanford University, Stanford, California, USA
,Stanford University, Stanford, California, USA
,Stanford University, Stanford, California, USA
,Stanford University, Stanford, California, USA
With the slowing of Moore’s law, computer architects have turned to domain-specific hardware specialization to continue improving the performance and efficiency of computing systems. However, specialization typically entails significant modifications to ...
Stanford University
,Stanford University
,Stanford University
High-level hardware generators have significantly increased the productivity of design engineers. They use software engineering constructs to reduce the repetition required to express complex designs and enable more composability. However, these ...
Stanford University
,University of California
,University of California
,Stanford University
Pairwise Whole Genome Alignment (WGA) is a crucial first step to understanding evolution at the DNA sequence-level. Pairwise WGA of thousands of currently available species genomes could help make biological discoveries, however, computing them for even ...
Stanford University, Stanford, CA, USA
,Tsinghua University, Beijing, China
,Stanford University, Stanford, CA, USA
,Stanford University, Stanford, CA, USA
,Stanford University, Stanford, CA, USA
,Stanford University, Stanford, CA, China
,Stanford University, Stanford, CA, USA
,Stanford University, Stanford, CA, USA
,Stanford University, Stanford, CA, USA
,Stanford University, Stanford, CA, USA
,Stanford University, Google, Stanford, CA, USA
,Stanford University, Stanford, CA, USA
We show that DNN accelerator micro-architectures and their program mappings represent specific choices of loop order and hardware parallelism for computing the seven nested loops of DNNs, which enables us to create a formal taxonomy of all existing ...
Stanford University & Tsinghua University, Stanford, CA, USA
,Stanford University, Stanford, CA, USA
,Stanford University & Google, Inc., Stanford, CA, USA
,Stanford University, Stanford, CA, USA
,Stanford University & Google, Inc., Stanford, CA, USA
The use of increasingly larger and more complex neural networks (NNs) makes it critical to scale the capabilities and efficiency of NN accelerators. Tiled architectures provide an intuitive scaling solution that supports both coarse-grained parallelism ...
Stanford University
,Stanford University
,Stanford University
In this paper, we propose an architecture for FPGA emulation of mixed-signal systems that achieves high accuracy at a high throughput. We represent the analog output of a block as a superposition of step responses to changes in its analog input, and the ...
Stanford University, Stanford, CA, USA
,Stanford University, Stanford, CA, USA
,Stanford University, Stanford, CA, USA
,Stanford University, Stanford, CA, USA
,Stanford University, Stanford, CA, USA
The high accuracy of deep neural networks (NNs) has led to the development of NN accelerators that improve performance by two orders of magnitude. However, scaling these accelerators for higher performance with increasingly larger NNs exacerbates the ...
Stanford University
,Stanford University and Movidius
,Stanford University
,Technion - Israel Institute of Technology
,Stanford University
DRAM energy is an important component to optimize in modern computing systems. One outstanding source of DRAM energy is the energy to fetch data stored on cells to the row buffer, which occurs during two DRAM operations, row activate and refresh. This ...
Stanford University
,Stanford University
,Stanford University
,Stanford University
,Stanford University
,Stanford University
Image processing algorithms implemented using custom hardware or FPGAs of can be orders-of-magnitude more energy efficient and performant than software. Unfortunately, converting an algorithm by hand to a hardware description language suitable for ...
Stanford University
,Stanford University
,Stanford University
,Stanford University
,Stanford University
,Stanford University
,Stanford University and NVIDIA
State-of-the-art deep neural networks (DNNs) have hundreds of millions of connections and are both computationally and memory intensive, making them difficult to deploy on embedded systems with limited hardware resources and power budgets. While custom ...
Stanford University
,Stanford University
,Stanford University
,Stanford University
Embedded wireless sensors, once deployed, may remain in active use for decades. At the same time, as motes come to dominate both the number of hosts and data traffic of the Internet, their security will become fundamental to general Internet security. ...
Stanford University, Stanford, CA, USA
,Stanford University, Stanford, CA, USA
,Stanford University, Stanford, CA, USA
,Stanford University, Stanford, USA
,Stanford University, Stanford, CA, USA
,Stanford University, Stanford, CA, USA
,Stanford University, Stanford, CA, USA
We describe Tethys, an energy-harvesting wireless water flow sensor that can monitor water use at a per-fixture level with the intention of associating water use with specific individuals. Tethys was motivated by recent efforts at Stanford University to ...
Palo Alto, CA
,Palo Alto, CA
,Google, Mountain View, CA
,Intel Corporation, Santa Clara, CA
,Stanford University, Stanford, CA
,Stanford University, Stanford, CA
General-purpose processors, while tremendously versatile, pay a huge cost for their flexibility by wasting over 99% of the energy in programmability overheads. We observe that reducing this waste requires tuning data storage and compute structures and ...
Stanford University
,Stanford University
,Stanford University
,MIT CSAIL
,Stanford University
,Stanford University
,Stanford University
,Stanford University
,Stanford University
Specialized image signal processors (ISPs) exploit the structure of image processing pipelines to minimize memory bandwidth using the architectural pattern of line-buffering, where all intermediate data between each stage is stored in small on-chip ...
Stanford University, Stanford, USA
,Microsoft Research, Mountain View, USA
,Stanford University, Stanford, USA
,Stanford University, Stanford, USA
All network devices must parse packet headers to decide how packets should be processed. A 64 x 10Gb/s Ethernet switch must parse one billion packets per second to extract fields used in forwarding decisions. Although a necessary part of all switch ...
Texas Instruments, Dallas, TX, USA
,Stanford University, Stanford, CA, USA
,Texas Instruments, Dallas, TX, USA
,Microsoft Research, Mountain View, CA, USA
,Stanford University, Stanford, CA, USA
,Texas Instruments, Dallas, TX, USA
,Texas Instruments, Dallas, TX, USA
,Stanford University, Stanford, CA, USA
In Software Defined Networking (SDN) the control plane is physically separate from the forwarding plane. Control software programs the forwarding plane (e.g., switches and routers) using an open interface, such as OpenFlow. This paper aims to overcomes ...
The more conservative the merging algorithms, the more bits of evidence are required before a merge is made, resulting in greater precision but lower recall of works for a given Author Profile. Many bibliographic records have only author initials. Many names lack affiliations. With very common family names, typical in Asia, more liberal algorithms result in mistaken merges.
Automatic normalization of author names is not exact. Hence it is clear that manual intervention based on human knowledge is required to perfect algorithmic results. ACM is meeting this challenge, continuing to work to improve the automated merges by tweaking the weighting of the evidence in light of experience.
ACM will expand this edit facility to accommodate more types of data and facilitate ease of community participation with appropriate safeguards. In particular, authors or members of the community will be able to indicate works in their profile that do not belong there and merge others that do belong but are currently missing.
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