ISPD

On behalf of the organizing committee, we are delighted to welcome you to the 32nd ACM International Symposium on Physical Design (ISPD). This is the third symposium that we have had online, which has helped us lower registration rates and expand our audience, more than doubling it. The symposium is over three days but with a shorter daily schedule, ending in the early afternoon to avoid being too late at night for attendees from time zones such as in Asia and Europe. As in 2021 and 2022, ISPD 2023 has a YouTube channel to view the talks, before, during, and after the conference, improving access to the presentations.

ISPD 2023 provides the forum to present leading-edge research results, exchange ideas, and promote research on critical areas related to the physical design of VLSI and other systems. Across the three days of ISPD 2023, we have 3 keynotes; 13 accepted papers; 22 regular invited talks; a panel on Wednesday with 5 panellists; and 3 speakers with longer talks in Professor Marek-Sadowska's commemorative session; and finally the ISPD 2023 contest results.

The regular papers in the ISPD 2023 program were selected after a rigorous, month-long, double-blind review process and virtual meetings, by the Technical Program Committee members. These papers exhibit the latest advancements in a variety of topics in physical design, including packing and legalization for heterogeneous FPGAs; global placement initialization; pin access analysis and awareness; detailed routing; reliability modeling and consideration in physical design (voltage drop, crosstalk, electromigration, thermal/stress migration); automated program repair to fix bugs in hardware description language (HDL) code; and hardware security-aware physical design against trojans and sidechannel attacks. A number of these papers utilize advanced mathematical programming, satisfiability problem solving, GPU acceleration, and reinforcement learning techniques.

The ISPD 2023 program is complemented by invited talks on topics ranging across quantum computing; analog design automation; 3D IC design, heterogeneous integration, and packaging; macro placement; machine learning, in particular reinforcement learning; hardware acceleration for electronic design automation (EDA) software; directed self-assembly for fabrication of nano-devices; electromigration and reliability. Additionally, we have a panel discussing challenges in EDA for domain-specific computing, for application-specific hardware to achieve substantially higher performance and lower power.

The conference features three keynote addresses. Monday's keynote is from Professor Alberto Sangiovanni-Vincentelli of the University of California, Berkeley. He will discuss automated design of chiplets, including an overview of current progress in chiplet design, providing crucial design considerations, and highlighting opportunities and challenges in this promising area. On Tuesday morning, Professor Burn J. Lin of National Tsing Hua University will explore immersion and Extreme UV (EUV) lithography, reviewing the history of lithography to how we have now achieved single-digit nanometer dimensions for circuit elements. The working principles, advantages, and challenges of immersion and EUV lithography will also be given in his talk. Wednesday's keynote is by Professor Anima Anandkumar of the California Institute of Technology and director of machine learning research at NVIDIA. She will detail their research providing state-of-the-art Fourier neural operators to efficiently solve partial differential equations (PDEs) on general geometries, demonstrating benefits in lithography software.